Senior Serdes Architect

Overview

Hybrid

We are at the forefront of Wideband Signal Processing™ delivering high-performance, low-power analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and other mixed-signal IP cores. These components are crucial for a wide array of modern applications, including artificial intelligence (AI) infrastructure and advanced wireless communications such as 5G networks and optical communications, automotive networking, LiDAR, radar systems, Sat Comm, Software Defined Radio (SDR), and other broadband communications.

Senior Ser Des architect and development lead focused on PAM4 ADC and DAC based wireline technologies. The successful candidate will work with customers to understand requirements, and lead the development of high-performance transistor-level design, starting from initial specification, through design and layout supervision, silicon evaluation and characterization, to final product introduction to market.

• Lead the development of high-performance transistor-level designs for PAM4 ADC and DAC wireline technologies from initial specification through product introduction to market.
• Work with customers to understand requirements and translate them into design targets.
• Oversee layout supervision and silicon evaluation and characterization.

• 10-20 years of experience in high-performance analog or mixed-signal IC development in advanced CMOS processes.
• Thorough familiarity with high-speed PAM4 architectures and topologies.
• Experience designing high-performance building blocks such as bandgap references, op-amps, comparators, oscillators, DLLs, PLLs, CTLEs, CDRs, etc.
• Thorough understanding of equalization techniques (analog and digital).
• Track record of successfully taking designs to production.
• Ability to work with customers to define products that address needs.
• Experience evaluating silicon on bench and familiarity with standard lab equipment.
• Strong intuitive and analytical understanding of transistor-level circuit design including noise and mismatch analysis.
• Experience with analog/digital behavioral modeling and/or synthesis of digital control blocks.
• Familiar with Cadence schematic capture, Virtuoso, Spectre and/or HSPICE circuit simulation tools.
• MATLAB understanding preferred but not mandatory.
• Familiar with designing circuits for electromigration and ESD compliance in submicron CMOS processes.
• Familiar with layout parasitic extraction tools and layout-dependent impairments in advanced CMOS processes.
• Ability to work independently, create and adhere to schedules.
• Strong written and verbal communication skills with ability to work with teams across geographic locations.
• Proactive in seeking help and sharing knowledge.

Contact: Mining The Knowledge Community

• Director

• Full-time

• Design, Research, and Engineering

• Semiconductor Manufacturing
• Computer Hardware Manufacturing
• Software Development