MTS, Interface Pathfinding Hardware Development Engineer

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Micron's Interface Pathfinding team drives performance-scaling innovation across circuits, signaling, packaging, and interconnects with a 3-5 year technology horizon.

As the Interface Pathfinding Hardware Development Engineer, you will own characterization for a high-speed interface test-chip program: the characterization plan and its success criteria, development of the characterization bench hardware and its automation, the measurement-uncertainty budget, and the correlation report proving the silicon matches the models. You will join a small, senior team spanning analog design, layout, digital design, and verification, working closely with the Chip Lead and the Signal Integrity and Physical Design engineers — driving decisions independently while consulting heavily with other experts across Micron.

This is a foundational hire for a growing program. Strong execution early is expected to lead to follow-on projects of increasing scope, team size, and characterization complexity — including an expanding mandate for AI-enabled engineering leadership across the organization.

• Characterization Planning:
  Derive the electrical characterization plan from the architecture specification and SI link budget before RTL freeze, each test case traceable to a specification parameter and success criteria.
• Design-for-Characterization:
  Author observability and test-access requirements (debug registers, trim exposure, loopback and pattern modes, analog test-mux) into the register map before RTL freeze.
• Measurement Infrastructure:
  Develop and own the characterization architecture from hardware and test board specifications through to the automated data acquisition framework.
• Measurement Uncertainty:
  Measure, calibrate, and de-embed characterization hardware to isolate device performance from measurement noise.
• Characterization:
  Serve as the program’s expert across link and timing integrity, power delivery, I/O-ring robustness, environmental corners, and first-silicon bring-up.
• Correlation and Debug:
  Co-author the per-revision sim-to-silicon correlation report with the SI engineer and lead the debug tiger team when silicon deviates from simulation.
• Tape-Out Readiness:
  Sign the characterization-readiness items on the tape-out checklist, then author the post-silicon characterization report and the correlation-gap table for the next test chip.
• Equipment Roadmap and Capability Building:
  Define bench capability against target data rates, represent findings to vendors, standards forums, and management, mentor junior engineers, and contribute to the IP portfolio.
• AI-Enabled Engineering Leadership:
  Serve as the Interface Pathfinding organization’s primary resource for agentic-AI workflow design and deployment. Architect, implement, and document AI-assisted development and characterization pipelines — including characterization plan generation, data analytics, and predictive modeling via sim-to-silicon correlation acceleration. Represent Micron’s AI-enabled characterization methodology to external partners, standards bodies, and internal leadership.

• MSEE with 10+ years (or BSEE with 12+ years) in semiconductor characterization or test engineering, including at least one program owned from plan through sign-off
• High-speed time-domain measurement including Rj/Dj separation and jitter transfer at multi-GT/s rates
• BERT and pattern generator/analyzer operation for link margining; switch-matrix…