Principal Signal Integrity Engineer

Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

At Micron, we transform how the world uses information to enrich life for all. As a global leader in memory and storage innovation, we develop technologies that accelerate intelligence and enable the next era of AI, ML, and advanced computing.

Micron’s Interface Pathfinding team operates at the leading edge of that mission — serving as a bridge between corporate strategy and engineering through forward-looking investigation and development of energy-efficient bandwidth solutions. Our work spans innovative circuit, signaling, packaging, and interconnect solutions with a 3–5 year technology horizon, grounded in rigorous analysis, hands‑on measurement, and a commitment to building a robust intellectual property portfolio.

As a Principal Signal Integrity Engineer, you will be a core technical contributor on a deliberately small, senior team united around the goal of preparing high-speed interface innovations for high-confidence product adoption.

Micron’s Interface Pathfinding team investigates and validates novel interconnect and signaling solutions for high-speed memory and die-to-die interfaces. The signal integrity scope is broad and analytically deep — spanning electrical modeling, channel analysis, and substrate evaluation — with an emphasis on original analysis rather than execution of established playbooks.

• Interconnect Modeling — Generating and validating electrical models for packages, substrates, and interconnects used in forward-looking feasibility studies
• Substrate & Packaging Evaluation — Assessing next‑generation substrate technologies and providing strategic direction on their signal integrity implications
• Channel & I/O Co‑Optimization — Performing SI analysis during feasibility studies and driving I/O + channel co‑optimization, including coordination with supporting organizations
• Design Rule Development — Driving progressive design rules that enable package and system‑level performance scaling
• Link Budgeting & Sim‑to‑Silicon Correlation — Establishing forward‑looking link budgets and developing methodologies that connect simulation predictions to measured silicon outcomes

• Interconnect Modeling:
  Own the generation and validation of interconnect models — from field solver extraction through time‑and‑frequency‑domain circuit simulation — serving as the authoritative source for model quality on the team.
• Technology Evaluation:
  Lead SI assessment of forward‑looking substrate and packaging technologies, translating physical characteristics into channel performance projections and strategic recommendations.
• Feasibility Analysis:
  Drive SI analysis during pathfinding studies, including I/O and channel co‑optimization, and provide direction to supporting organizations when analysis is distributed.
• Design Rule Definition:
  Develop and champion progressive package and system‑level design rules grounded in electromagnetic analysis and simulation data.
• Link Budgeting:
  Define forward‑looking link budgets and establish the sim‑to‑silicon correlation methodologies that give the team and product programs confidence in pre‑silicon predictions.
• Cross‑Disciplinary Engagement:
  Collaborate across Signal Integrity, Circuit and Chip Design, Packaging R&D, and System Integration — translating SI findings into actionable guidance for partner teams.
• Design Documentation:
  Author analysis reports, modeling methodology documents, and…