Principal Design AI Engineer San Jose, California, Posted

## Principal Design AI Engineer San Jose, California, United States of America
** Our vision is to transform how the world uses information to enrich life for
* all*.
** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

As a Principal Design Engineer in the NVE Design Engineering organization at Micron Technology, Inc., you will drive the transformation of NAND circuit development through design automation, agentic circuit-design enablement, and environment transition!
** What’s Encouraged Daily!
*** Implementing core Xpath, Ypath and Array design during project execution and work with project teams integrating the Core schematics into the fullchip schematics, validating design performance and functionalities by running block and chip level simulations using standard industry simulators and mentor other engineers for the same.
* Implementing analog and mixed signal circuit design (charge pumps, op amps, DACs, ADCs, linear regulators, oscillators, bandgap, LDO, thermometers, page buffers, PDNs, level shifters, IO buffers, RTL, Verilog) to meet specifications, validating design performance and functionalities by running block and chip level simulations using standard industry simulators and mentor other engineers for the same.
* serve as a technical authority across analog/core teams, solving sophisticated technical problems at the intersection of circuit behavior, modeling, simulation methodology, and automation reliability.
* Develop and productize agentic enablement for circuit design, including AI/LLM-assisted flows that support:  + environment setup and self-healing configuration,  + guided simulation and debug,  + intelligent corner planning and coverage closure,  + automated schematic/layout checks and review assistance,  + documentation synthesis and knowledge retrieval from internal sources,  + block/subsystem/full-chip verification (analog/mixed-signal), including reproducible run recipes, golden reference management, and regression gating criteria.
* Integrate automation with project execution, partnering with circuit designers, firmware, validation, and architecture teams to align tooling with achievement needs and deliver measurable cycle-time reduction.
* Collaborate with multi-functional team members   (Product Engineering, Test, Probe, Process Integration, Assembly, Marketing) to ensure automation and environmental choices support manufacturability, testability, reliability, time-to-market, and customer happiness.
*
* Minimum Qualifications:

*** MS (PhD preferred) in electrical engineering required. 8+ years of NAND design relevant proven experience required with proficient knowledge of Nand Flash memory read, program and erase algorithms
* Proficiency in analog/mixed signal circuit design (page buffers, block selectors, Xdecoder, Ydecoder, bias table and waveforms, PDNs, level shifters, charge pumps, op amps, DACs, ADCs, linear regulators, oscillators, bandgap, IO buffers, RTL, Verilog)
* Proficiency in analog/mixed signal circuit layout (page buffers, block selectors, Xdecoder, Ydecoder, bias table and waveforms, PDNs, level shifters, charge pumps, op amps, DACs, ADCs, linear regulators, oscillators, bandgap, IO buffers, RTL, Verilog)
* Proficient fundamentals in semiconductor and device physics and analog/mixed-signal circuit design. An understanding of semiconductor reliability issues including CHC, NBTI, stress, and snapback, as well as Electro-migration (EM) and IR analysis.
* Proficiency in circuit verification and optimization, layout planning, parasitic extractions of the circuits, experience guiding layout.…