DRAM Test Structure Intern: Layout & Verification
Listed on 2026-10-07
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Engineering
Test Engineer, Engineering Design & Technologists
Micron Technology is seeking a highly motivated Engineering Intern to join the DRAM Build Enablement and Test Structure Engineering team in Boise, Idaho. You will contribute to the development, layout, verification, and analysis of semiconductor test structures used to characterize advanced DRAM technologies, gaining hands-on experience with industry-leading EDA tools and silicon evaluation techniques.
You will write automation scripts in Python or Tcl to boost engineering efficiency,
For the DRAM Test Structure Intern:
Layout & Verification position at Micron, we are reviewing applications now.
The advertised compensation is 28.000 - 41.000.
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the DRAM Test Structure Intern:
Layout & Verification role in the description above.
We appreciate your interest in this position.
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