Senior ASIC Design Engineer – ML & Network Acceleration
Listed on 2026-10-16
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Engineering
Systems Engineer, Hardware Engineer
Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration.
Minimum qualifications include a Bachelor's degree in a relevant field and 8+ years in micro-architecture/RTL development or SoC integration, with RTL using Verilog/System Verilog and HLS. Public compensation ranges from $178,000 to $250,000 per year, plus bonus, equity and benefits.
Step into the Senior ASIC Design Engineer – ML & Network Acceleration role at Meta in Boise, , United States and grow with us.
This role, Senior ASIC Design Engineer – ML & Network Acceleration at Meta, could be your next career step.
Are you ready to take on the Senior ASIC Design Engineer – ML & Network Acceleration role at Meta?
We would love to welcome a new Senior ASIC Design Engineer – ML & Network Acceleration to our team in Boise, , United States.
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