DTCO Intern: DRAM Physical Design & PPA Optimization
Listed on 2026-10-17
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Engineering
Electronics Engineer, Process Engineer, Manufacturing Engineer, CAD/ AutoCAD/ Mechanical Design
Micron Technology, Inc. invites applications for an Intern in DRAM Technology Physical Design and Block-Level PPA Optimization in Boise, Idaho. The role focuses on implementing standard cell blocks, benchmarking PPA, and supporting timing closure using industry tools and AI-enabled automation.
You will gain hands-on experience in physical design, timing analysis, and design verification while collaborating with DTCO teams to optimize silicon outcomes and power efficiency.
This is a strong role to take on the DTCO Intern: DRAM Physical Design & PPA Optimization role at Micron Technology, Inc.
We invite applications for the DTCO Intern: DRAM Physical Design & PPA Optimization position located in Boise, , United States.
The following opening is for a DTCO Intern: DRAM Physical Design & PPA Optimization with Micron Technology, Inc.
Our group is growing, and we are hiring a DTCO Intern: DRAM Physical Design & PPA Optimization in Boise, , United States.
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