Senior ASIC/FPGA Architect - RTL & Tape- Lead
Listed on 2026-10-18
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Engineering
Systems Engineer, Hardware Engineer, Electronics Engineer
Anysilicon is seeking an experienced ASIC Lead Engineer to drive RTL design and oversee the full ASIC design lifecycle. The role requires hands-on technical leadership, independence, and collaboration across teams to ensure tape-out of complex silicon.
Ideal candidates bring extensive ASIC/FPGA design experience, especially in advanced nodes, and can define architecture, lead RTL development, and manage verification activities. DoD clearance and US citizenship are required.
The Senior ASIC/FPGA Architect - RTL & Tape-Out Lead role at Anysilicon is now open for applications in Boise, , United States.
Please review the full job details above before applying.
If your experience matches this role, we encourage you to apply.
All applications are reviewed carefully by our team.
The position is based in Boise, , United States.
This opportunity is part of our work in IT & Technology, Engineering.
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