Photonics Layout Engineer

Photonics Layout Engineer at Psi Quantum, Palo Alto, California (remote). A mid-level full time position in the 3200 - Photonics Integration team, listed under hardware engineering.

Quantum computing promises to solve many important problems that could never be solved on any conventional computer. At Psi Quantum, we’re building a general-purpose silicon photonic quantum computer to tackle these very problems.

We are looking for an energetic, highly motivated Photonic Layout Engineer who will be responsible for the design, layout, and verification of photonic integrated circuits (PIC) for foundry fabrication.

You will in a high pace environment, working across hardware and design enablement teams to translate photonic designs and process requirements into manufacturable layouts. The role combines hands-on PIC layout with python-based or commercial-based layout tools (GDSFactory, Synopsys, Candence Photonics, etc) with verification and automation.

Master’s degree, PhD, or equivalent in Electrical, Computer Engineering, Material Science, Physics.

Note:

Psi Quantum will only reach out to you using an official Psi Quantum email address and will never ask you for bank account information as part of the interview process. Please report any suspicious activity to  .

Actual compensation may vary outside of these ranges and is dependent on various factors including, but not limited to, a candidate's qualifications, relevant education and training, competencies, experience, geographic location, business needs, and internal equity. Your recruiter can share more details about the salary range applicable to your location during the hiring process.

• Zone 1 - Bay Area and NYC
• Zone 2 - Examples include Los Angeles and Washington DC
• Zone 3 - Examples include Austin, Chicago, and Sacramento
• Zone 4 - Examples include Nashville and Phoenix/Tempe and many remote locations

• Prepare and maintain photonic layouts from individual components to complex circuits, using passive and active components.
• Drive foundry tapeouts from implementing layouts to physical verification, including design rule checking (DRC), layout versus schematic (LVS), fill, and density checks.
• Develop and maintain layout infrastructure and automation tools that improve layout quality and workflow efficiency.
• Contribute to PDK development by implementing and validating layout components and design rules.
• Prepare clear, complete documentation and handoff materials for tapeouts.

• 2 years of relevant work or academic research experience in integrated photonics and layout.
• Experience creating layouts for photonic integrated circuits and understanding how photonic components and circuits map to physical layout.
• Experience with one or more photonic layout tools, such as GDSFactory, Synopsys, Cadence, or similar.
• Strong Python programming skills, including experience scripts for layout generation, automation or numerical analysis.
• Experience with collaborative code management tools such as Git.
• Experience with silicon photonic manufacturing processes, foundry design rules, and tapeout workflows.
• Proven team player with an ability to work effectively across departments, sites, time zones.
• Excellent verbal and written communication skills.
• Strong analytical and detail oriented problem-solving skills.