Senior CAD Engineer - Layout​/Verification​/Simulation Boise, Idaho, Posted ago

Position: Senior CAD Engineer - Layout/Verification/Simulation Boise, Idaho, United States of America + 1 more Posted 8 hours ago
## Senior CAD Engineer - Layout/Verification/Simulation Boise, Idaho, United States of America Apply Now Find out how well you match with this jobJob :
JR116732
** Our vision is to transform how the world uses information to enrich life for
* all*.
** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
** Responsibilities
* ** Develop, enhance, and debug CAD tools, automation, and flows for custom IC design, layout, simulation, and verification.
* Contribute to one or more functional areas: layout automation, physical verification, circuit simulation, or digital implementation.
* Integrate, evaluate, and qualify in-house and commercial EDA tools in production environments.
* Partner with design, layout, verification, and process teams to resolve workflow and tool-integration challenges.
* Identify gaps in current tools and flows, and evaluate EDA industry offerings to improve quality, performance, and efficiency.
* Provide training, documentation, and production support to end users.
* Apply AI/ML and agentic AI to CAD automation, debugging, and user support.
* Develop clean, scalable software and mentor engineers to support their technical growth.
* Lead technical projects and contribute to CAD methodology roadmaps.##
** Minimum Qualifications
*** Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent.
* 5+ years of industry experience in
** CAD, EDA, or semiconductor design.
*** Experience developing or supporting EDA tools and flows in at least one area:
** custom layout, physical verification, circuit simulation, or digital implementation.
*** Experience with IC design CAD tools for schematic capture, layout, simulation, or verification.
* Proficiency in
** Python
* * and at least one additional language, such as SKILL, Tcl, Perl, C, or C++, plus Linux/Unix and shell scripting.
* Solid CMOS and VLSI fundamentals, with clear communication and practical debugging skills across global teams.##
** Preferred Qualifications
*** Experience with Cadence Virtuoso and SKILL, including layout automation or parameterized cell (PCell) development.
* Experience with Calibre design rule checking (DRC) and layout versus schematic (LVS) flows, or rule-deck development in SVRF.
* Experience with circuit simulators such as Spectre, HSPICE, Fine Sim, Prime Sim, VCS, or Xcelium.
* Experience with RTL-to-GDS tools such as Fusion Compiler, Innovus, Prime Time, or Formality.
* Experience with parasitic extraction tools such as StarRC or Quantus.
* Experience applying AI/ML, large language models, or agentic AI to engineering workflows.
* Experience with source control, automated testing, and release management.
* Knowledge of DRAM, HBM, NAND, or emerging memory development.  The US base salary range that Micron Technology estimates it could pay for this full-time position is:$ - $ a year Additional compensation may include benefits, bonuses and equity.  Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations.

Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base…