Senior DRAM IO & Clock Design Architect

Micron Technology, a world leader in memory and storage, seeks a Principal/ MTS IO/Clock Design Engineer to lead high-speed IO and clocking circuit design for DRAM IP. You will drive modeling, verification and optimization, addressing jitter, timing and performance at full-chip level.

Relocation to Micron’s Boise headquarters is required. The role collaborates with design, SI, and process teams, mentoring engineers and advancing next-generation process nodes.

We invite applications for the Senior DRAM IO & Clock Design Architect position located in Boise, , United States.

Consider building your career as a Senior DRAM IO & Clock Design Architect at Micron Technology, Inc.

The Senior DRAM IO & Clock Design Architect position in the IT & Technology, Engineering field is open for applications.

We have an opening for a Senior DRAM IO & Clock Design Architect in Boise, , United States within IT & Technology, Engineering.