Principal Digital ASIC Design Engineer

Overview

Draper is an independent, nonprofit research and development company headquartered in Cambridge, MA. The 2,000+ employees of Draper tackle important national challenges with a promise of delivering successful and usable solutions. From military defense and space exploration to biomedical engineering, lives often depend on the solutions we provide. Our multidisciplinary teams of engineers and scientists work in a collaborative environment that inspires the cross-fertilization of ideas necessary for true innovation.

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Draper Laboratory is seeking talented and motivated individuals to tackle challenging engineering problems in advanced digital IC design. As a Senior Digital ASIC Designer, you will be responsible for designing high-performance digital ASICs in advanced technologies. You will be responsible for implementing designs from RTL through synthesis. You will work in multi-disciplinary teams with opportunities to learn, grow and contribute to a variety of projects in different application areas.

• Design and simulate circuits at transistor-level to implement architecture and requirement specifications
• Contribute to system-level design
• Optimize hardware designs for performance, power, and cost
• Evaluate the hardware feasibility of complex algorithms and requirements
• Independently contribute to complex chip architectures and designs
• Independently drive solutions to complex problems - develop requirements, propose ways forward when customer requirements are unclear or incomplete, and adapt appropriately to changes in requirements
• Contribute to business development and proposal activities
• Develop, document, and teach best practices to less experienced engineers
• Perform or guide physical layout, including floor-planning, and simulate circuits using extracted parasitics, contribute to design-for-test development
• Perform other duties as assigned

• Proficiency in integrated circuit design
• Understanding of integrated circuits, semiconductors, and general computer architecture
• Ability to write detailed design specifications
• Ability to lead multi-disciplinary technical teams
• Excellent verbal and written communication skills
• Excellent mathematical skills
• Excellent organizational skills and attention to detail
• Excellent time management skills with the proven ability to meet deadlines
• Strong analytical and problem-solving skills
• Ability to prioritize tasks
• Demonstrate strong organization, planning, and time management skills to achieve program goals

Requires a bachelor s degree in Engineering, or related field. Masters degree preferred.

Requires 7-10 years of experience with a bachelor s degree, or 5-10 years of experience with a master s degree in ASIC Hardware Engineering or related.

• Experience with low power circuit design
• Experience with CMOS advanced nodes below 32nm
• Experience with radiation-hardened electronics

• Applicants should possess solid skills in front-end digital systems design with experience in design flows from Cadence or Synopsys.
• Be fluent in System Verilog, Verilog or VHDL and familiar with LINT, simulation and synthesis.
• Familiarity with architectures for secure systems design, e.g., cryptographic encoders / decoders or tagged processor architectures is a plus.
• Demonstrated experience with successful tape-outs at advanced nodes is desired. Experience leading and managing design teams is also desired.

This position requires onsite work in Cambridge, MA.

Applicants selected for this position will be required to obtain and maintain a U.S. Security Clearance.

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Job Location - City:
Cambridge

Job Location - State:
Massachusetts

Job Location - Postal Code:

The US base salary range for this full-time position is $95,000.00 - $

Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the…