Silicon Test Engineer - Automotive SoC

We are building terahertz imaging radar for automotive perception. Our sensor architecture combines millimeter-wave transmit and receive front-ends, a high-channel-count data conversion front-end, and an integrated radar signal processor. These are automotive parts headed for AEC-Q qualification and volume production with Tier 1 customers.

Our next-generation sensor SoC is a multi-chip module that co-packages a high-channel-count mixed-signal data conversion die with a digital compute die carrying a real-time processor, DSP cluster with FFT acceleration, GPU, functional safety monitor, hardware security module, external DRAM interface, and automotive Ethernet. The two dies communicate over a high-speed die-to-die link across a fine-pitch, automotive-grade interposer.

We are looking for an engineer who will own the product test for this module.

You will define and drive wafer probe and final test for both dies and for the integrated package - building the test programs, owning the test hardware, and managing our contract manufacturers, OSATs, and test houses to get from first silicon to qualified, yielding, production-tested parts. This is a hands‑on role with real scope: you set the test strategy, you sit at the prober during bring‑up, and you own the AEC‑Q campaign that makes the part shippable.

• Lead bench and ATE bring‑up of both the die and the co‑packaged module as parts return from fab and assembly.
• Own the wafer probe and ATE plan for the module, from strategy through execution.
• Debug first‑silicon issues alongside design, DFT, and package teams; drive failures to root cause across analog, digital, and interconnect domains.
• Bring up the die‑to‑die link at test: link training, sideband channel behavior, BER and margining, and the known‑good‑die criteria that gate assembly.

• Define wafer sort flows and test coverage for both a mixed‑signal data conversion die and a digital compute die - two very different test problems on the same program.
• Specify and qualify probe cards with leading probe card suppliers; own pinout sign‑off against the bump map, first‑article inspection, and probe‑mark and contact‑resistance qualification.
• Build known‑good‑die screening rigorous enough to protect module assembly yield, including per‑die traceability, OTP/eFuse programming for device  wafer coordinates, and calibration data write.
• Set up wafer map handling, bin definitions, and yield reporting from the sort floor.

• Develop and own production ATE test programs covering IDDQ, functional, scan (stuck‑at and at‑speed), MBIST, DC para metrics (VOH/VOL, IOH/IOL, ZOH/ZOL), serial interface timing, static and dynamic current, PLL and clocking, and temperature sensor trim and calibration.
• Own analog and mixed‑signal test methodology for the data conversion path: ENOB, SNR/SNDR, INL/DNL, offset and gain trim, channel‑to‑channel matching and crosstalk, and converter test modes.
• Translate designer‑supplied simulation collateral and DFT deliverables into production patterns; close the loop with design and DFT on testability gaps before tapeout, not after.
• Design and bring up load boards and characterization boards; drive socket selection and qualification with package and socket vendors, including thermal and contact‑life considerations at automotive temperature extremes.
• Own full PVT characterization across corners, bench‑to‑ATE correlation, Gage R&R, and datasheet limit derivation - you turn characterization data into guard banded production limits.
• Working with contract manufacturers and test partners
• Serve as the primary technical interface to our external test partners for hardware and program bring‑up, program transfer, and production ramp.
• Wri…