Member of Technical Staff, Modeling

We are seeking a Member of Technical Staff, Functional and Performance Modeling to develop functional and performance models for our scale-up network-attached memory expansion device for AI accelerators.

You’ll work as part of our silicon architecture team to perform functional and performance modeling. You should have experience exploring design tradeoffs, validating performance assumptions, and identifying bottlenecks early in the development cycle. This role is well-suited for engineers who enjoy reasoning from first principles, working with incomplete information, and co-exploring the design space as hardware and software evolve together.

This role will be performed onsite from one of our offices in Santa Clara, CA or Boston, MA.

• Build and maintain system-level (e.g., rack-scale) and chip-level performance models for high-bandwidth data movement between devices operating in the scale-up domain.
• Model workloads from software memory access patterns through data distribution in the network and all the way down to on-device memory channels.
• Work day-to-day with silicon architects, system designers, and workload owners to align performance expectations and constraints.
• Identify performance bottlenecks, scaling limits, and sensitivity points across compute, memory, and interconnects in end-to-end workload settings.
• Clearly communicate modeling assumptions, limitations, and conclusions to both technical and non-specialist stakeholders.

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a closely related field.
• 5–10+ years of experience in performance modeling for data movement devices: NICs, memory expansion cards (e.g. CXL), IPU/DPU, NoC.
• Ability to reason across multiple abstraction layers, from architectural details to system-level performance behavior.

• Prior experience modeling performance for networking protocols with memory semantics.
• Familiarity with shared memory systems and frameworks (e.g. CUDA VMM).
• Familiarity with modern AI/ML technical stack from a workload perspective: large language model inference and sharding, KV caching, serving system (e.g., continuous batching).
• Experience with scale-up and high-bandwidth interconnects (e.g. NVLink or similar technologies).
• Experience with modeling memory subsystems

• Competitive salary with performance-based bonus and early-stage equity grant
• 100% employer-paid Health, Dental, and Vision coverage for you and your dependents
• 401(k) match with immediate vesting, and access to financial advisors to help you reach your financial goals
• 100% employer-paid Life, Disability, and AD&D insurance, plus a fitness stipend and wellness & mental health perks
• Generous PTO: 20 vacation days, 15 company holidays (including 3 floating days of your choosing)
• Daily lunch stipend
• Enterprise-level Claude & ChatGPT access with a generous token budget
• Well-equipped, sunny offices in Santa Clara, CA & Cambridge, MA with on-site parking and EV charging; on-site fitness center in Santa Clara; gym discounts near our Cambridge office
• Visa sponsorship and relocation assistance to one of our office hubs
• A collaborative, continuous-learning environment with smart, dedicated colleagues building the next generation of high-performance computing architecture

• Impact: Humanity stands at the dawn of a new industrial revolution driven by AI—one with the potential to redefine how we live on this planet. We are tackling a fundamental challenge at the infrastructure layer: unlocking greater AI capability while dramatically improving efficiency. The work we do here compounds across state-of-the-art AI models, systems, and real-world…