Intern, RISC-V CPU

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC‑V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible.

We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Our team developed a high performance RISC‑V CPU from scratch, and share a passion for AI and a deep desire to build the best compute platform possible.

This posting spans multiple roles within the RISC‑V team. One application, one recruiter screen - then we match you to the specific team and location that fits best. What each sub‑team does:

• RTL Design: Implement and debug CPU‑block RTL and contribute to microarchitecture and RTL infrastructure. Final years of bachelors or later
• Implementation Engineer: Translate CPU microarchitecture into a synthesizable, performant design. Work with the RTL team to drive performance, power and area improvements.
• Design Verification: Verify high‑performance, out‑of‑order RISC‑V CPUs across ISA and microarchitecture features.
• Formal Verification: Develop assertions and formal‑analysis flows to identify corner‑case hardware issues. Austin‑only role.
• Core Performance Verification: Validate CPU performance through workload bring‑up, simulation, emulation, and bottleneck analysis.
• Design Verification Software & Infrastructure: Build scalable software, automation, CI/CD, and test infrastructure for CPU verification.
• Platform Software: Develop low‑level software, firmware, testing, and automation for high‑performance RISC‑V CPUs.

This role isonsite, based out of Austin, TX or Boston, MA or Fort Collins, CO or Santa Clara, CA.

• Currently pursuing a BS, MS, or PhD in EE, ECE, CS, CE or related field
• Strong academic performance with hands‑on related coursework, project or work experience.
• Interest in RISC‑V, CPU architecture, AI/ML hardware, verification, performance, or low‑level software.
• Strong debugging, analytical, communication, and collaboration skills.
• Ability to learn new tools and work in an on‑site engineering environment
• Interest or exposure with AI tools to accelerate development and workflows.

• Strong foundational exposure to one or more of the following key areas:
• HDLs (such as System Verilog), computer architecture, or RTL design and debugging concepts.
• Programming or scripting skills in Assembly, C/C++, Python, or Perl.
• Design verification, formal analysis, simulation, test benches, or coverage analysis.
• CPU microarchitecture, out‑of‑order pipelines, memory systems, or performance modeling.
• Familiarity with Linux, Git, CI/CD pipelines, firmware, or low‑level system software.

• Hands‑on experience with modern, out‑of‑order RISC‑V CPU microarchitecture design and implementation.
• Advanced design verification methodologies, including formal analysis, simulation, and testbench development.
• Low‑level platform software, firmware, and system‑level initialization for high‑performance processors.
• Performance analysis, bottleneck identification, and optimization techniques on custom silicon environments.

This internship opportunity is available throughout our 3 terms with the following corresponding recruitment cycles:

• Fall Term:
  Sept–Dec work term, Jan–Aug recruit.

Please note these timelines are for reference only. Actual timelines may vary.

Compensation for all interns…