Senior Design Verification Engineer - Emulation & UVM Lead

A leading technology firm is seeking a Design Verification Engineer in Boulder, Colorado. The role demands familiarity with RTL design in Verilog and extensive experience in Design Verification and Debug. Applicants need to demonstrate competence in developing verification methodology and owning DV tasks from testing to using emulations. A Bachelor’s or higher degree in a relevant field and U.S. citizenship are required.

This is a full-time, on-site position, fostering innovation within a dynamic engineering team.
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