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FPGA Design Engineer

Job in Boulder, Boulder County, Colorado, 80301, USA
Listing for: Jobs via Dice
Full Time position
Listed on 2025-12-23
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 82900 - 146165 USD Yearly USD 82900.00 146165.00 YEAR
Job Description & How to Apply Below

Job Description

Lockheed Martin Space is seeking a Field Programmable Gate Array (FPGA) Design Engineer to work on space-based mission processing capabilities at the edge. The role involves evolving mission processing applications of remote sensing payloads onto flight hardware for onboard mission processing operations, using the Vivado Design Suite and hardware design languages VHDL and Verilog. The engineer will work alongside research scientists, software engineers, and other FPGA engineers on the APEX (Advanced Programs and Exploitation) team.

Responsibilities
  • Develop an understanding of mission processing code written in C++ and implement it for hardware processing.
  • Develop, integrate, and test processor subsystem features and interfaces in FPGA hardware.
  • Generate requirements, create FPGA code, and develop test benches.
  • Ensure compliance with government security investigation and classified information access requirements.
  • Work at Lockheed Martin Space’s Boulder, Colorado office.
Basic Qualifications
  • Bachelor of Science or higher in Electrical Engineering, Computer Engineering, or a related discipline, or equivalent experience/combined education.
  • Ability to obtain a TS/SCI clearance.
  • Strong understanding of HDL languages (VHDL & Verilog).
  • Experience designing with Xilinx Vivado.
Desired Skills
  • Proficiency in MATLAB & C++.
  • Digital logic design experience.
  • Experience interfacing FPGAs with processors.
  • Experience with Vitis Model Composer and MATLAB HDL Coder.
  • Familiarity with Xilinx platforms and tools.
  • Knowledge of FPGA concepts such as clock domains, memory hierarchies, and routing.
  • Demonstrated experience in the ASIC/FPGA life cycle (architecture, design, simulation, verification, validation, integration & test).
  • Knowledge of space‑grade/qualified FPGAs and ASICs.
Remote Work

The position offers part‑time remote telework, allowing a portion of the work schedule to be performed remotely and the remainder at a designated Lockheed Martin facility. Specific weekly schedules will be discussed during the hiring process.

EEO Statement

Lockheed Martin is an equal opportunity employer. Qualified candidates will be considered without regard to legally protected characteristics.

Pay Range

Annual base salary range (varies by location): $82,900 – $146,165 (excluding most major metropolitan areas). For other locations, the range will reflect the final work location. Salary is a general guideline and may be adjusted based on responsibilities, experience, education, and market conditions.

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