ASIC & FPGA Engineer Senior

ASIC & FPGA Engineer Senior Staff

Lockheed Martin Space is seeking a Field Programmable Gate Array (FPGA) Design Engineer to work on space‑based mission processing capabilities at the edge. The role will evolve mission processing applications of remote sensing payloads onto flight hardware for onboard mission processing operations. The engineer will leverage Vivado Design Suite and HDLs (VHDL, Verilog) to deploy processing code and algorithms onto flight hardware, working alongside research scientists, software engineers, and other FPGA engineers on the APEX (Advanced Programs and Exploitation) team.

• Develop understanding of mission processing code written in C++ and implement for hardware processing.
• Integrate and test processor subsystem features and interfaces in FPGA hardware.
• Generate requirements, create FPGA code, and develop test benches.
• Perform integration and validation activities across the FPGA/ASIC lifecycle.

• Bachelor of Science or higher in Electrical Engineering, Computer Engineering, or related discipline (or equivalent experience).
• Ability to obtain a TS/SCI clearance.
• Experience with VHDL & Verilog HDL languages.
• Experience designing with Vivado.
• Proficiency in Matlab & C++ (desired).
• Digital logic design experience.
• Experience interfacing FPGAs with processors.
• Experience with Xilinx tools and platforms.
• Knowledge of FPGA concepts (clock domains, memory hierarchies, routing).
• Familiarity with space‑grade/qualified FPGAs and ASICs.

Lockheed Martin is an equal opportunity employer. Qualified candidates will be considered without regard to legally protected characteristics.

Boulder, Colorado. Flexible work schedule with partial remote (part‑time remote telework) and part at Lockheed Martin facility.

Position will close in 90 days. Apply within 5–30 days of the requisition posting date for optimal consideration.