Senior ASIC RTL Front-End Engineer — SoC Innovation
Listed on 2026-10-07
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Engineering
Hardware Engineer, Electronics Engineer, Systems Engineer, Test Engineer
Capgemini Engineering seeks an Expert Front-End ASIC RTL Designer to join a team working on advanced semiconductor technologies. You will design, develop and debug ASIC IPs, collaborating across design, verification and software teams to deliver high-quality SoCs.
The role involves RTL design in Verilog/System Verilog/VHDL, IP integration at the SoC level, and adherence to DFT, CDC, RDC, Lint, and UPF guidelines in a dynamic engineering environment.
We are seeking a motivated Senior ASIC RTL Front-End Engineer — SoC Innovation to join Capgemini Engineering in England, United Kingdom.
Full responsibilities and requirements are described in the listing above.
Learn more about the Senior ASIC RTL Front-End Engineer — SoC Innovation role in the description above.
We appreciate your interest in this position.
Join Capgemini Engineering and contribute to our ongoing work.
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