Principal Verification Engineer

Location: Bedminster

We have an exciting opportunity in Cambridge for a Principal Verification Engineer to lead verification of open-source digital designs, including Open Titan, RISC-V cores, OTBN, crypto accelerators, and peripherals .

What Youll Do :
Lead design, implementation, and debugging of System Verilog/UVM test benches Develop verification plans, tests, and coverage strategies Mentor engineers and drive best practices Collaborate with partners to support successful tapeouts Contribute to test and CI infrastructure Requirements: 8 years in digital design verification with leadership experience Strong System Verilog/UVM skills Full verification lifecycle experience through tapeout C and/or Python for test automation Git/Git Hub and team collaboration experience Nice to Have:
Formal verification, RISC-V/ISA experience, security verification, post-silicon debug