Principal IC Layout Engineer

Our client is hiring for a Principal IC Layout Engineer to join their expanding silicon team based in Bristol. Hybrid working is available, with 1-2 days a week in the office.

As a leading British Semiconductor company our client offers a fantastically varied and interesting workload, delivering challenging design projects within various market sectors from automotive to satellite communications and RF, working in all manner of technology nodes. The Principal IC Layout Engineer will have responsibility for translating schematic designs into layout solutions to achieve the specification and project schedule, and will be critical to the work of the front‑end IC design team also.

For this role we are looking for an IC Layout expert with some additional front‑end design knowledge. Requirements include:

• Strong experience in full‑custom analog layout, chip finishing, and tape‑out
• Expertise in integrating digital blocks into analog
• Experience with physical verification processes including DRC, LVS, Antenna
• Skills in Cadence Virtuoso L/XL and Mentor Calibre for layout design and verification
• Knowledge of power grid planning, ESD validation, and performing Power, IR drop, and EM analysis across a wide range of technology nodes
• Eligibility to work in the UK

On offer is a competitive base salary and full benefits package including discretionary bonus.

For more details, please contact Caroline Pye.