Verification Engineer; f​/m​/div

Staff Verification Engineer

As a Staff Verification Engineer on our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life.

• Develop a deep understanding of complex IPs and contribute to the verification of these IPs
• Be responsible for developing System Verilog - UVM test bench components for IPs
• Define and write a functional coverage model, write constrained random tests to hit coverage targets
• Ensure the test bench meets sign‑off targets, including coverage, functional safety, and test bench qualification
• Debug failing test cases to identify root causes
• Represent verification perspective and collaborate in Design and Concept meetings, contributing to the verification strategy and architecture of IP test benches
• Proactively improve verification efficiency and mitigate risks early

• A Bachelor's degree in Electrical/Electronic Engineering or equivalent
• At least 3‑5 years of experience in Verification, preferably at the IP level, with System Verilog - UVM
• Knowledge in UVM and SVAs, System Verilog
• Experience with verification platform and framework development
• Proven experience of IP verification including delivering to metric targets
• Capability to understand complex design specifications, derive features and test bench architectures from concept, and use industry‑standard EDA tools
• Fluency in English (mandatory)

We embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect, and tolerance, and are committed to giving all applicants and employees equal opportunities. We base our recruiting decisions on the applicant’s experience and skills.

Contact:
Rita Costa, Linked In