Senior Design Verification Engineer

Company

Qualcomm Technologies International Ltd

Engineering Group, Engineering Group > ASICS Engineering

Qualcomm invents breakthrough technologies that transform how the world computes, connects, and communicates. Today, our inventions are the foundation for life‑changing products, experiences, and industries.

Qualcomm’s Voice and Music group is a leading player in wireless earbud, headset, and smart speaker market. We develop and deliver hardware, software and applications that bring together the very latest wireless and audio technologies to create industry leading audio voice and music products.

We are seeking a Senior Staff Design Verification Engineer to provide technical leadership and end‑to‑end ownership of verification for complex low‑power, mixed‑signal IPs and SoCs. This role is based in Bristol or Cambridge and is suited to an engineer with demonstrated impact beyond a single project or block.

As a Senior Staff Design Verification Engineer, you will set verification direction, influence design and system decisions, and ensure delivery of robust, production‑quality silicon. You will work at the intersection of architecture, digital design, analog, firmware, and systems, and act as a technical reference point for both execution and methodology.

This role requires a balance of hands‑on technical depth, strategic ownership, and people influence, with accountability for verification outcomes across programs.

• Own and drive verification strategy, test planning, and methodology for complex digital and mixed‑signal IPs and subsystems.
• Partner closely with system and architecture teams to shape requirements, identify verification risks early, and ensure alignment on quality goals.
• Lead verification planning and reviews to ensure functional completeness, coverage closure, and sign‑off readiness.
• Architect and evolve scalable, reusable verification environments supporting low‑power techniques and mixed‑signal designs.
• Define and implement complex, system‑level test scenarios that reproduce real‑world and silicon‑observed failures.
• Drive debug and root‑cause analysis of complex issues, from simulation through regression and power‑aware flows, tracking issues to closure.
• Own DV execution outcomes for assigned projects, ensuring predictable delivery, risk transparency, and driving high verification quality.
• Use a variety of EDA tools, automation, and workflows to increase verification efficiency and robustness.
• Mentor and coach engineers in stimulus creation, checkers, assertions, coverage models, and debug best practices.
• Act as a technical leader within the DV community, influencing standards, best practices, and knowledge sharing.
• Communicate clearly and credibly with senior technical leadership and cross‑functional stakeholders.
• Model a positive, inclusive, and ownership‑driven mindset, contributing to a strong and collaborative engineering culture.
• Bring energy and enthusiasm to solving complex problems as part of a diverse, multi‑site team.

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

• Exposure to Mixed‑Signal, Low‑Power verification with SV Real number models, V‑models.
• Expert in HVL such as System Verilog, UVM.
• Experience with formal verification (Jasper, VC Formal).
• Experience of design best practices and HW/FW interfaces.
• Strong working knowledge of digital design and SoC architecture.
• Scripting in Perl, TCL or Python.
• Gate‑Level Simulation and Debug — 0‑delay, timing annotated.
• Experience in Low power aware Verification.
• Debugging regression failures and tracking to closure through bug tracking process.
• Exposure to System C / HLS flows will be a bonus.
• It will be good to add AI knowledge, e.g. LLMs, coding…