Senior Packaging Design Engineer

About OLIX

AI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten‑year‑old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade.

The OLIX Decode Accelerator 1 (DX‑1) is the first accelerator architected specifically for decode. Rack‑scale co‑design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance.

At OLIX, the performance of our technology depends not only on silicon design, but on how effectively that silicon is packaged, integrated, and scaled into products. As we move from early architecture and prototype development toward productisation, the Senior / Staff Packaging Engineer will play a critical role in defining and delivering the packaging solutions that enable our ASICs to become high‑performance systems.

This is a hands‑on, high‑impact engineering role focused on front‑end package design, ASIC‑to‑substrate integration, and advanced 2.5D and 3D packaging. You will work across silicon, substrate, package, and board‑level interfaces to ensure package solutions meet performance, manufacturability, and integration requirements from concept through to production readiness.

You will lead packaging engineering across the full development flow, including package architecture, detailed design, layout, simulation, and product readiness. This includes defining package design methodologies, owning substrate design, delivering PI/SI simulations, and supporting substrate and PCB integration as needed. Working closely with the ASIC team, you will translate die requirements into package solutions that are electrically robust, manufacturable, and ready for system integration.

A key part of the role will be owning the end‑to‑end package design flow for next‑generation AI hardware, including package architecture, bump and substrate design, package layout, high‑speed and power delivery integration, PI/SI‑driven optimisation, and substrate/PCB co‑design.

• Own package design activities for ASIC‑to‑substrate integration, including bump/pad mapping, substrate escape, interconnect strategy, package floor planning, and stack‑up definition
• Lead the development of 2.5D and 3D package architectures, including multi‑die integration, chiplet‑style interfaces, and heterogeneous integration approaches
• Define package structures that meet electrical, thermal, mechanical, reliability, and manufacturability requirements
• Translate silicon and system requirements into practical package design rules, routing constraints, and implementation strategies
• Drive package technology selection based on performance, risk, manufacturability, cost, and scalability

• Own or lead the full package design flow, from concept definition through detailed design, analysis, layout, verification, release, and manufacturing support
• Develop and review package layouts including die placement, substrate routing, power/ground distribution, high‑speed interface breakout, and physical integration constraints
• Own and execute PI/SI simulation activities to validate signal integrity, power delivery, and package performance, translating results directly into design improvements and sign‑off decisions
• Support package‑to‑board co‑design, including substrate layout and PCB layout/interface definition where required
• Ensure strong alignment between die, package, substrate, and board‑level implementation
• Oversee package database management, design reviews, sign‑off, and release readiness

• Use package design tools such as Cadence Allegro X APD, or equivalent to develop and maintain advanced package and substrate layouts
• Establish and improve package design libraries, templates, rules, and workflows to support efficient and repeatable development
• Drive layout reviews,…