Verification Engineer

Great opportunity for a Senior staff Verification Engineer to join a global R&D network.

As a Staff Verification Engineer, you will take ownership of IP verification topics for cutting-edge designs of the future of the company’s Automotive division, while working together with the team who has a proven track record in successful IP deliveries into Automotive Microcontrollers.

• Define a verification plan, requirements mapping, develop an SV-UVM test benchand solve related potentially complex problems
• Debug failing test casesto root cause
• Define and write afunctional coverage model
• Participate inreviews to ensure test bench meets quality and sign-off targets, including coverage, functional safety and test bench qualification
• Proactively help increase efficiency of verification activities and mitigate risks early
• Contribute to enhancing Verification strategy and architectureof IP test benches

• At least5 years of experience in verification, withIP level as mandatory and Subsystem level as an advantage
• Expertise in hardware verification languages, particularly
  
  System VerilogandUVM, with the ability to design efficient and effectivetest bench architectures
• Familiarity withEDA toolsfor Design and Simulation, as well asscripting languages such asPythonor Perl
• Knowledge of functional safety standards, includingISO
  26262andASIL-D requirements