Senior SoC Physical Verification Lead - Tapeout Signoff
Listed on 2026-10-21
-
Engineering
Hardware Engineer, Test Engineer
Aion Silicon Ltd. seeks an experienced SoC Physical Verification Engineer to lead signoff for next generation logic and memory-centric designs.
You will ensure tapeout-ready silicon by performing DRC, LVS, ERC, PERC, DFM, and reliability checks, driving methodology and signoff with PD, CAD, RTL, and foundry teams. You will develop automation, AI-assisted workflows, and regression infrastructure while collaborating with EDA vendors and fabs, including direct TSMC interaction from kickoff to
Step into the Senior SoC Physical Verification Lead
- Tapeout Signoff role at Aion Silicon Ltd in West of England, England, United Kingdom and grow with us.
We are looking to fill the Senior SoC Physical Verification Lead
- Tapeout Signoff position at Aion Silicon Ltd in West of England, England, United Kingdom.
The Senior SoC Physical Verification Lead
- Tapeout Signoff role at Aion Silicon Ltd is now open for applications in West of England, England, United Kingdom.
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).