Senior Verification Engineer – RTL/UVM, Hybrid
Listed on 2026-10-21
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Engineering
Test Engineer
Acceler Comm Ltd. is seeking a Senior Verification Engineer in Bristol, UK to lead RTL verification across ASIC/FPGA designs. You will develop verification plans, build System Verilog/UVM environments, and drive robust validation prior to deployment. Hybrid working is available.
The role requires 3+ years in digital verification, strong System Verilog/UVM skills, Linux scripting, and a collaborative mindset to work across multiple teams.
This is a great opening to take on the Senior Verification Engineer – RTL/UVM, Hybrid Work role at Acceler Comm Ltd.
The position is based in West of England, England, United Kingdom.
This opportunity is part of our work in Engineering.
The advertised compensation is 60.000 - 90.000.
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the Senior Verification Engineer – RTL/UVM, Hybrid Work role in the description above.
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