Senior ASIC Verification Engineer — SystemVerilog/UVM Expert
Listed on 2026-10-26
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Engineering
Test Engineer, Quality Engineering
Empiric is seeking 5+ ASIC Verification Engineers for a global semiconductor manufacturing project. You will drive verification strategy, build advanced UVM/System Verilog test benches, and own verification plans for SoC/IP blocks.
The role is based in Bristol or Cambridge with a 12-month rolling contract and a start in December. You should bring strong UVM/System Verilog expertise, experience with constrained-random stimulus, coverage-driven verification, and good collaboration with RTL teams to
Step into the Senior ASIC Verification Engineer — System Verilog/UVM Expert role at Empiric in West of England, England, United Kingdom and grow with us.
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the Senior ASIC Verification Engineer — System Verilog/UVM Expert role in the description above.
We appreciate your interest in this position.
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