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Senior Memory Layout Designer – Vancouver, BC (Infosys)
Advance your technical expertise as a Senior Memory Layout Designer with Infosys in Vancouver, BC. Focus on high-performance memory architectures while collaborating with an agile team. This pivotal role demands a robust background in Compiler and Custom Memory Layout with 5+ years of experience. You will work on developing innovative memory designs, incorporating FinFET technology, and ensuring DRC compliance.
Key Responsibilities- Collaborate on overall memory path layout design
- Design and develop custom memory leafcell libraries
- Optimize layout designs for performance improvement
- Conduct essential physical verification and debugging
- Maintain clear communication with team members
- Bachelor's degree or equivalent related experience
- Minimum 5 years in memory layout design
- Robust knowledge of memory architectures and FinFET principles
- Proficient in Cadence Virtuoso and Calibre
- Authorized for unrestricted work in Canada
Showcase your layout capabilities and contribute to the future of memory design at Infosys.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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