Principal RTL Design Engineer

Job Overview

The Mixed Signal Development Group delivers high‑performance analog, digital, and mixed‑signal IP to various divisions within Microchip. Leveraging advanced CMOS processes, the team designs mixed‑signal integrated circuits for wireline applications, enabling seamless connectivity between Microchip products and the external world. As a member of the group, you will work closely with architects, digital design engineers, verification engineers, firmware engineers, and cross‑functional teams.

• Participate in the full ASIC design cycle, including design, verification, backend implementation, silicon bring‑up, and debugging.
• Design RTL using Verilog/System Verilog, integrate IP blocks, and implement supporting logic (clock/reset, JTAG, DFT, SRAMs, etc.).
• Run clock‑domain crossing (CDC) analysis, lint checks, and power simulations.
• Work with verification teams or participate in verification, review, optimize, and execute verification plans; debug design and simulation issues.
• Collaborate with the backend team on STA timing closure, analyze timing critical paths, and resolve timing issues; run trial synthesis to estimate logic depth and area early in the design cycle.
• Partner with Product Engineering on characterization planning and execution, DFT-related tasks, create test plans, test configuration, and provide debug support.
• Develop C‑based drivers for DDR/Flash PHY, perform simulation‑based validation, and support silicon bring‑up in the lab.
• Produce high‑quality design, verification, and test documentation.

• Bachelor’s/Master’s/PhD in Electrical Engineering, Computer Engineering/Science, or related field.
• 2–10 years of ASIC development experience (level dependent).
• Strong experience in RTL design and verification using Verilog, System Verilog, or VHDL.
• Hands‑on debugging experience with lab equipment (oscilloscopes, logic analyzers).
• Experience or knowledge in C/C++ and scripting/automation (Python, Perl, TCL, Shell).
• Working knowledge of DDR and Flash Controller/PHY/memory is an asset.
• Strong problem‑solving skills with ability to work independently and proactively.
• Ability to collaborate effectively in a team‑oriented environment.

Annual base salary range: $86,000–$186,000 (dependent on location, skills, and experience). A total compensation package includes competitive base pay, restricted stock units, and quarterly bonus payments. Health benefits begin day one. Retirement savings plans are offered. The industry‑leading IESPP program includes a 6‑month lookback feature.

0%–25% travel required.