Principal RTL Design Engineer at Microchip

Join Microchip's Mixed Signal Development Group as a Principal RTL Design Engineer, focusing on high-performance analog and digital circuit design. Engage in a dynamic embedded environment, requiring expertise in Verilog/System Verilog for ASIC development.
In this key role, you will drive the full ASIC design cycle, from initial design through verification to silicon bring-up. Collaborate effectively with a range of professionals, including architects, digital design engineers, and firmware engineers, contributing to integrated circuit solutions. Your efforts will ensure robust and efficient designs across wireline applications.

Key Responsibilities:

• Participate in full ASIC design cycle activities

• Design RTL using Verilog/System Verilog and integration

• Perform clock-domain crossing analysis and power simulations

• Collaborate with verification teams for effective debugging

• Work with backend team on timing closure and synthesis
Requirements:

• Bachelor’s/Master’s/PhD in Electrical Engineering or related field

• 2–10 years of ASIC development experience

• Proficient in RTL design verification and debugging

• Experience with lab equipment and simulation tools

• Knowledge of C/C++ and scripting automation
Support cutting-edge designs with your RTL expertise at Microchip.
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