Senior Engineer - Design Job Burnaby area,BC Canada,Engineering

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our ;

we affectionately refer to it as the and it’s won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over without a great team dedicated to empowering innovation. People like you.

Visit our page to see what exciting opportunities and company await!

Job Description:

Microchip’s Datacenter Solutions (DCS) group is looking for an experienced Design Engineer to join the storage controller team developing the next generation of advanced storage controller devices fueling the big data revolution. In this senior role you will take technical ownership of complex subsystems—driving them from architecture and RTL design through verification, silicon bring-up, and post-silicon support—while acting as a subsystem lead and technical mentor to other engineers.

Your responsibilities will include, but are not limited to:

Responsibilities

Act as subsystem lead: own the architecture, micro-architecture, and RTL implementation of complex digital subsystems (100K to 10M+ gates), coordinating schedule, scope, and technical direction across the team.

Design, code, and integrate synthesizable RTL in System Verilog/Verilog and VHDL, ensuring designs meet functional, timing, area, and power targets.

Maintain and support existing/legacy RTL and IP, and extend it with new features and enhancements while preserving stability, backward compatibility, and design quality.

Architect and integrate subsystems using standard on-chip interconnect protocols such as AXI/AMBA, including bus fabric, bridging, and interface compliance.

Implement robust clock domain crossing (CDC) schemes and low-power design techniques (clock gating, power gating, multi-voltage/UPF flows) to meet power, performance, and reliability goals.

Develop and review subsystem and device-level verification plans, and drive verification closure using System Verilog, UVM, and Formal verification methodologies.

Implement SAS and SATA protocol logic and ensure compliance with applicable storage protocol standards and specifications.

Apply strong debug skills to track down and resolve complex design, verification, and integration issues, working closely with design, verification, emulation, validation, and firmware teams to ensure timely resolution.

Lead and support post-silicon bring-up, characterization, and debug; reproduce and root-cause silicon issues in the lab and drive fixes or workarounds.

Mentor junior engineers, perform design and code reviews, and contribute to design methodology, reuse, and quality improvements.

Interface with cross-functional teams (architecture, firmware, validation, product, and customers) to align requirements and deliver robust, production-quality silicon.

Requirements/

Qualifications:

Bachelor’s or Master’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.

Significant professional experience (typically 7+ years) in digital ASIC/SoC design and verification.

Strong RTL design and verification expertise in System Verilog and VHDL, including UVM-based and/or Formal verification methodologies.

Hands-on experience with AXI/AMBA (and related…