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Job Description:
The Architecture Co-Verification team (ACOV) is an exciting, fast-paced team responsible for enabling HW/FW development and co-verification of state-of-art System-On-Chip (SoC) devices using industry-leading HW emulators (such as Cadence Palladium and Protium). The team is deployed in all aspects of SoC development phases from architectural exploration to post-silicon validation, HW/FW co-development, pre-silicon functional co-verification, pre/post-silicon performance testing, power analysis, and critical post-silicon investigations.
As an Emulation Engineer, you will be working closely with architects, hardware designers, firmware engineers, and verification teams throughout the SoC development process.
This is a role for a versatile engineer that enjoys the challenges of HW/FW co-development and system-level co-verification using leading-edge HW emulators and FPGA platforms.
It’sa high-visibility role that will develop a wide range of skills and exceptional problem-solving abilities.
Responsibilities could include but are not limited to the following:
Managing amulti-location, cross functional team of engineers and technicians
Planning and developing a common test ecosystem across pre/post silicon
Using Jira to plan and track project tasks and report results
Troubleshoot and resolve complex problems in embedded multi-core real-time systems executing emulation test plans.
Utilizationof test and defect tracking tools to document and report on verification progress and product quality
Effectively present technical information to small teams of engineers.
Requirements/
Qualifications:
BS/MS/PhD in degree or higher in Electrical/Electronic Engineering or Computer Engineering
12.5+ years of experience in leading FPGA/ASIC/EDA development,simulationand verification projects.
2+ years' experience with one or more serial storage protocols such as SAS, SATA,NVMe, CXL and thorough knowledge of the PCIe interface.
In-depth knowledge of CXL protocols.
Experience working with large scale FPGA solutions
Thorough understanding of digital design, RTLcodingand simulation
Prior knowledge and experience in HDL languages (Verilog, VHDL andSystemVerilog)
Working knowledge of C/C++,TCLor Perl/Python languages.
Excellent verbal and writtencommunicationalskills.
Effective team player, collaborator, and a great motivator forteam.
Ability to work in a multi-location, cross functional team
Proficiencyin lab equipment usage for test and debug
Microcontroller programming skills are desirable
Desirable:
Cadence infrastructure support and maintenance flows
Proficient in using Agile methodologies and Bug tracking tools
Optional Desired Skills that can be included/replaced above-
Experience with RAID HBA’s, SAS Controllers and their associated Software Testing Strategies.
Experience with Computer System I/O hierarchies and…
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