Yield Enhancement Engineer

Join TSMC Washington and help power the future of global technology. As the world’s leading semiconductor foundry, TSMC partners with industry pioneers to drive advancements in critical sectors, including healthcare, automotive, and renewable energy. At our Washington facility, we unite precision manufacturing with a culture of continuous innovation. We are seeking driven professionals who share our commitment to integrity, excellence, and collaboration to join us in shaping the next generation of technology.

A Yield Enhancement Defect Engineer at TSMC Washington bridges the gap between raw process data and customer satisfaction. The primary mission is to identify, analyze, and eradicate physical or electrical defect sources that limit wafer yields. Working inside a high-volume manufacturing cleanroom ecosystem, engineers use advanced metrology, data analytics, and cross‑departmental collaboration to prevent production line deviations (excursions) and optimize mature CMOS process node.

Responsibilities include:

• Defect Reduction & Yield Improvement
  - Root-Cause Analysis:
  Use physical failure analysis (PFA), statistical data monitoring, and electrical characterization to proactively uncover complex tool or loop-level defect modes.
  - Defect Road mapping:
  Establish aggressive defect-reduction goals and optimize manufacturing steps alongside integration and module teams.
  - Continuous Improvement (CIP):
  Lead baseline yield expansion and baseline defect-density reduction tasks to drive structural manufacturing performance.
• Metrology & Inline Inspection Management
  - Tool Ownership:
  Act as the technical owner of inline defect inspection, review, and scan equipment (such as optical systems).
  - Recipe Optimization:
  Program, tune, and advance inline recipes to improve defect detection sensitivity while minimizing false counts.
  - Statistical Process Control (SPC):
  Utilize advanced SPC algorithms to catch tool or process deviations early before they compound into high-cost product scrap events.
• Cross-Functional Collaboration & Customer Support
  - Module & Integration Liaison:
  Collaborate directly with Etch, Thin Film, Lithography, and Diffusion module engineers to isolate tool‑induced particle or defect signatures.
• Customer Technical Partnership

- Translate raw inline defect or yield metrics into actionable engineering data to support key global customer product run-rates and address specific manufacturing concerns.

Requirements:

• Bachelor’s, Master’s, or Ph.D. in Materials Science, Electrical Engineering, Chemical Engineering, Physics, or related STEM fields.
• Comprehensive understanding of semiconductor physics, CMOS fabrication flows, failure analysis methodologies, and advanced statistical modeling software.
• Team player with strong communication skills
• Detail oriented with excellent trouble shooting and problem solving skills
• Project management capability
• Familiarly with SPC concept practice and statistical data analysis
• Programming or semiconductor fabrication experience a plus
• Self-starting highly motivated individuals
• 0-2 years related experience

Responsibilities included:

• Transferring new products and technologies from TSMC headquarters.
• Reviewing daily WAT and online/offline abnormal signal and implementing containment and preventative actions.
• Collaborating with FAB engineering team to improve yield and WAY stability and reduce process defects.
• Providing technical support to mixed signal customers.

Personal Attributes:

• Convey complex technical concepts.
• Initiative-driven with priorities and responsibilities to support our needs.
• Excels as both a team player and a leader, encouraging collaboration.
• Motivated by achieving measurable results and improving performance.
• Maintains focus and accuracy when working on intricate…