Senior Digital Design Engineer

Cambridge, UK | Full-time | Permanent | Hybrid

Salary: £70,000 to £90,000 DOE+ Bonus + Benefits

Riverlane’s mission is to master quantum error correction (QEC) and unlock a new age of human progress. From advances in material and climate science to complex chemistry simulation for new drug design, quantum computers will help humanity solve some of its most important challenges. But without QEC, the industry’s defining technical challenge, such breakthroughs can never be achieved. Riverlane is the world leader in QEC technology.

QEC is a complex problem that requires a range of skills, talent and passion.

We have a fantastic opportunity for an experienced Digital Design Engineer to join us as we build the world’s first quantum error correction (QEC) stack. Don’t have a background in quantum computing? Not a problem! This cutting‑edge technology requires a wide range of skills and disciplines, including classical computing skills. You will learn quantum computing along the way.

As a senior‑level Digital Design Engineer at Riverlane, you will help develop a multi‑FPGA, low‑latency, high‑throughput system that needs to perform complex operations, in a predictable and guaranteed way. You will use your knowledge and expertise to support more junior engineers, interact with software and identify novel solutions to our challenging problems.

This is an exceptional opportunity to join Riverlane's Hardware team, where you will develop cutting‑edge decoding algorithms and tackle complex data routing and processing challenges while maximizing system throughput and minimizing latency.

Our mission is exciting, but complex. It requires teams with a wide range of skills and perspectives, that communicate well and collaborate effectively to achieve truly innovative solutions.

You will thrive in an environment where knowledge sharing and continuous learning are the norm. We are moving fast in a brand new market, where requirements can change quickly as the technology evolves, so the ability to adapt is critical.

• Performance and area optimisation of our RTL
• Designing deeply pipelined modules capable of operating reliably at very high clock speeds
• Reviewing specifications and RTL produced by junior engineers

• Experience with state‑of‑the‑art FPGA platforms (e.g. AMD/Xilinx MPSoCs/RFSoCs, Altera Stratix 7 or Stratix 10)
• Proven professional experience in at least one of the following areas:
  • Implementation of modern classical decoders on FPGA/ASIC e.g. LDPC, turbo‑codes
  • Architecture of System on Chip solutions, with at least one CPU and custom accelerators
  • Large‑scale, complex systems on FPGA/ASIC
  • Proven capability to test, debug and improve complex systems
  • Ability to convert product requirements into technical specifications to document and share your work
  • A curious nature and a passion for learning and continuous improvement
  • Excellent communication skills, with the ability to work both independently and collaboratively as part of a team

• Experience with ASIC environments (