CPU; RISC-V Researcher

We are seeking a highly skilled and experienced Staff Research Scientist with strong ISA extensions experience. This is a high-level research and development role.

• Analyse dynamic language overhead: Profile V8 and ArkTS interpreter/JIT to identify operations that consume disproportionate cycles (type checks, inline cache misses, garbage collection barriers, dynamic dispatch, deoptimisation)
• Design ISA extensions: Propose new instructions or architectural features that accelerate common dynamic language patterns while maintaining backward compatibility and security boundaries
• Model in architectural simulators: Implement proposed extensions in GEM5
• Collaborate on RTL implementation: Work with digital design teams to refine instruction encoding, pipeline integration, and verification requirements
• Publish and patent: Document novel contributions through internal technical reports, conference papers, and patent applications

• Deep understanding of CPU microarchitecture
  : pipelines, out-of-order execution, branch prediction, memory hierarchy, ISA design principles
• Experience with architectural simulation (GEM5, Sniper, ZSim, or proprietary tools)
• Strong C/C++ and systems programming skills
• Comfortable working in Linux environments with Git, Make, scripting
• Equivalent industry experience (5+ years in CPU architecture, compilers, or language runtimes) welcomed
• PhD or MSc in Computer Science, Computer Engineering, or Electrical Engineering preferred