Server CPU Physical Design Engineer, Senior​/level

Job Overview

Qualcomm Technologies International Ltd is seeking talented Physical Design Engineers to join the Nuvia CPU team in Cambridge, UK. The team develops next‑generation, high‑performance, power‑efficient custom CPU cores for advanced compute and server‑class platforms. The role ranges from Senior Engineer to Staff Engineer, with responsibilities, ownership, and technical leadership scaling with experience.

• Own or contribute to CPU block implementation from RTL/netlist to GDS, including synthesis, floor planning, power planning, placement, clock tree synthesis, routing, optimization, ECOs, and sign‑off.
• Drive timing closure and physical implementation convergence across multiple modes, corners, and operating conditions.
• Work on high‑performance, low‑power CPU designs with demanding performance, power, and area targets.
• Debug and resolve complex implementation issues related to timing, congestion, clocking, routing, IR drop, power integrity, EM, ECO closure, DRC/LVS, and physical verification.
• Collaborate closely with RTL, architecture, circuits, CAD, SoC, and post‑silicon teams to improve design quality, implementation efficiency, and product performance.
• Evaluate and contribute to the design process from concept through productization, including architecture definition, feasibility analysis, pre‑silicon design and verification, and post‑silicon validation.
• Develop and enhance physical design flows, automation, and methodologies to improve productivity and quality of results.
• Use data‑driven analysis to identify implementation bottlenecks, improve design convergence, and push PPA beyond standard targets.
• For Staff‑level candidates, provide technical leadership, mentor engineers, define implementation strategies, and drive closure of critical CPU blocks or methodology initiatives.

• Strong experience in physical design implementation, including synthesis, floor planning, placement, CTS, routing, timing closure, ECOs, and sign‑off.
• Strong understanding of static timing analysis and timing closure methodologies, and trade‑offs between timing, power, area, congestion, and routability.
• Knowledge of high‑performance and low‑power implementation techniques.
• Hands‑on experience with industry‑standard EDA tools for synthesis, place and route, STA, power analysis, physical verification, and sign‑off (e.g., Genus, Innovus, Fusion Compiler, Prime Time, Tempus, Voltus, Red Hawk, Conformal).
• Ability to debug complex physical design issues across timing, congestion, clocking, routing, power, and verification domains.
• Scripting and automation experience using TCL, Python, or Perl.
• Strong communication skills and the ability to work effectively in a global, cross‑functional engineering environment.

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with relevant experience in ASIC, CPU, or physical design implementation.
• Master’s degree with relevant hardware engineering experience, or a PhD with relevant CPU/ASIC/physical implementation experience.

• Physical design experience on CPU cores, high‑performance compute blocks, or timing‑critical ASIC designs.
• Experience working in advanced semiconductor process nodes, especially 7nm and below.
• Strong understanding of CPU PPA optimization and design convergence.
• Experience with low‑power design techniques, clock optimization, useful skew, standard‑cell library usage, and physical‑aware optimization.
• Knowledge of power integrity, IR drop, EM analysis, and power sign‑off.
• Experience with timing ECOs and late‑stage design closure across large scenario sets.
• Understanding of CPU microarchitecture, logic design, or circuit‑level implementation considerations.
• Experience developing physical design methodology, automation, or productivity‑enhancing flows.
• For Staff‑level candidates, proven ability to lead complex technical work, influence cross‑functional teams, and mentor other engineers.

• Strong physical design fundamentals and enthusiasm for solving difficult implementation problems.
• Passion for pushing performance,…