Server CPU Physical Design Integration Engineer, level

Overview

Qualcomm is looking for an experienced CPU Physical Design Integration Engineer to join the Nuvia Data Center CPU team in Cambridge, UK. This team focuses on developing next‑generation, high‑performance, and power‑efficient custom CPU technologies for advanced compute and server platforms, driving innovation across the industry. In this position you will play a key role in the physical design, integration, and verification of high‑frequency CPU designs, collaborating closely with microarchitecture, RTL design, CAD, circuit design, block‑level physical design, and SoC‑level physical design to deliver production‑ready designs.

• Own final CPU layout database implementation, integration, and verification of high‑frequency next‑generation data center CPU designs.
• Drive block partitioning, floorplan implementation, and pin placement strategies.
• Work with SOC and other IP teams to ensure all technical, interface, and integration requirements are met.
• Partner with CAD and physical design teams to develop and improve flows for chip‑level integration, validation, and analysis.
• Collaborate with project team members to identify and resolve issues that arise during the design cycle, applying learnings to future product cycles.
• For Staff‑level candidates, provide technical leadership, mentor engineers, influence cross‑functional methodology, and drive resolution of complex and critical integration challenges.

• Deep CPU‑specific expertise across structural and physical design, including synthesis, timing closure, multi‑power‑domain analysis, structured placement, and routing.
• Experience collaborating with leading EDA vendors to develop, enhance, and optimize tool capabilities for designing high‑speed, low‑power, synthesizable CPU cores.
• Optimizes CPU design to improve product‑level parameters such as power, frequency, and area.
• Hands‑on involvement in developing, refining, and automating physical design methodologies and implementation flows.
• Strong leadership and communication skills, able to work effectively with global, cross‑functional distributed teams across architecture, RTL, CAD, circuit design, physical design, SoC, and verification disciplines.
• Proficiency in scripting and automation to improve productivity and debug efficiency, including adoption of GenAI‑driven initiatives where applicable.
• Experience with industry‑standard EDA implementation and signoff flows for physical design, timing analysis, power analysis, and physical verification.

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with relevant experience in hardware engineering, CPU design, physical design, clock design, or implementation.
• Master’s degree in a related field with relevant experience in hardware engineering, CPU design, physical design, clock design, or implementation.
• PhD in a related field with relevant experience in CPU design, physical implementation, clock design, or circuit‑aware methodology.

• Experience leading or contributing to CPU, GPU, or large SoC physical design integration from early floor planning through final GDS tapeout.
• Strong background in top‑level or chip‑level physical design, including floor planning, partitioning, pin placement, power planning, clock distribution, IP integration, and final layout database assembly.
• Hands‑on experience with hierarchical physical design methodologies, including top‑down planning, budgeting, block integration, timing convergence, and physical convergence.
• Experience working with advanced semiconductor process nodes, especially 7nm and below.
• Strong understanding of place and route, clock tree synthesis, structured placement, routing optimization, congestion analysis, and design closure methodologies.
• Familiarity with power‑aware implementation techniques, including multi‑voltage domains, power gating, clock gating, IR drop mitigation, EM analysis, and power integrity closure.
• Experience integrating hard IP, memory macros, mixed‑signal blocks, PLLs, clocking structures, and third‑party IP into large‑scale CPU or SoC designs.
• Abili…