Server CPU Clock Physical Design Engineer, level

Job Overview

Qualcomm is seeking an experienced CPU Clock Physical Design Engineer to join the Nuvia Data Center CPU team in Cambridge, UK. The team develops next‑generation, high‑performance, power‑efficient custom CPU technology for advanced compute and server‑class platforms that will transform the industry. In this role you will define, implement, and optimize best‑in‑class clock generation and distribution solutions for high‑frequency CPU designs, working closely with micro‑architecture, RTL design, CAD, circuit design, block‑level physical design, and top‑level physical design teams.

• Define and drive the overall clock generation and clock distribution methodology for next‑generation data center CPU designs.
• Collaborate with microarchitecture, RTL, CAD, circuit, block‑level physical design, and top‑level physical design teams to understand, implement, and validate CPU clocking requirements.
• Architect, implement, and optimize low‑skew, low‑power clock networks using clock H‑trees, clock mesh, and clock spines methodologies.
• Partner with CAD and physical design teams to develop and deploy clocking techniques that optimize skew, latency, clock power, timing margin, routability, and design convergence.
• Use SPICE simulation and circuit‑level analysis to validate clock circuits, clock paths, and electrical behavior across process, voltage, and temperature conditions.
• Analyze and debug clock‑related timing, power, noise, variation, and physical implementation issues across multiple modes, corners, and operating conditions.
• Provide feedback and guidance to block‑level and top‑level physical design engineers on required clocking fixes, optimization opportunities, and signoff risks.
• Collaborate with PLL, timing, power, CAD, and implementation teams to align clock source assumptions, jitter budgets, clock uncertainty, and signoff methodology.
• Develop, document, and improve clock construction, analysis, and validation flows for future CPU generations.
• For Staff‑level candidates, provide technical leadership, mentor engineers, influence cross‑functional methodology, and drive resolution of critical clocking challenges.

• Strong experience in the construction and analysis of low‑skew and low‑power clock generation and distribution networks.
• Hands‑on experience with clock distribution structures and methodologies such as Clock H‑tree, Clock Mesh, Clock Spines.
• Deep understanding of CTS, clock balancing, insertion delay, skew optimization, useful skew, clock power reduction, and clock latency tradeoffs.
• Good understanding of device physics, RC delay, signal integrity, variation, and electrical effects that influence clock quality and timing robustness.
• Proficiency in SPICE simulation and analysis for circuit design, clock‑path validation, and electrical verification.
• Strong understanding of static timing analysis and the interaction between clock architecture, timing closure, jitter, uncertainty, OCV/AOCV/POCV, setup/hold closure, and signoff quality.
• Ability to debug complex clocking issues across implementation, timing, power, noise, variation, and circuit domains.
• Experience with industry‑standard EDA implementation and signoff flows for physical design, timing analysis, power analysis, and physical verification.
• Strong communication skills and ability to work effectively with global, cross‑functional engineering teams.

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with relevant experience in hardware engineering, CPU design, physical design, clock design, or implementation.
• OR Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with relevant experience in hardware engineering, CPU design, physical design, clock design, or implementation.
• OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with relevant experience in CPU design, physical implementation, clock design, or circuit‑aware methodology.

• Experience defining or deploying clock methodology…