Server CPU Physical Design Integration Engineer, level

Position: Server CPU Physical Design Integration Engineer, Staff level
Company:

Qualcomm Technologies International Ltd Job Area:

Engineering Group, Engineering Group  ASICS Engineering General

Summary:

Job Overview Qualcomm is looking for an experienced CPU Physical Design Integration Engineer to join the Nuvia Data Center CPU team in Cambridge, UK . This team is focused on developing next-generation, high-performance, and power-efficient custom CPU technologies for advanced compute and server platforms, driving innovation across the  this position, you will play a key role in the physical design, integration, and verification of high-frequency CPU designs.

You will collaborate closely with cross-functional teams, including microarchitecture, RTL design, CAD, circuit design, block-level physical design, and SoC-level physical design, to deliver production-ready designs.

Your responsibilities will span the full CPU physical design flow, including synthesis, floor planning, partitioning, power planning, IP integration, clock and power distribution, reliability analysis, power and noise analysis, static and dynamic power integrity, layout verification, and electrical rule checking.

This role offers the opportunity to impact CPU architecture and design methodologies from early planning stages through implementation, signoff, and silicon validation.

The position is offered at the Staff Engineer level, with responsibilities, ownership, and technical leadership commensurate with your experience.

Key Responsibilities will include

As a Server CPU Physical Design Integration Engineer , you will:

Own Final CPU Layout database Implementation, Integration and Verification of high frequency next-generation data center CPU designs.

Driving block partitioning, floorplan implementation and pin placement strategies.

Work with SOC team and other IP teams to ensure all technical, interface and integration requirements are met.

Partner with CAD and physical design teams to develop and improve flows for chip-level integration, validation and analysis.

Working collaboratively with project team members to identify and resolve issues which arise during the design cycle and take the key learnings into the next product cycle.

For Staff-level candidates, provide technical leadership, mentor engineers, influence cross-functional methodology, and drive resolution of complex and critical Integration challenges.

Required Skills and Experience We are seeking candidates with strong experience in CPU physical design implementation Domain, preferably with experience delivering complex, high-performance CPU designs.

The ideal candidate will have:

Deep CPU-specific expertise across multiple areas of structural and physical design, including synthesis, timing closure, multi-power-domain analysis, structured placement and routing.

Experience collaborating closely with leading EDA vendors to develop, enhance, and optimize tool capabilities for designing high-speed, low-power, synthesizable CPU cores.

Optimizes CPU design to improve product level parameters such as power, frequency, and area.

Hands-on involvement in developing, refining, and automating physical design methodologies and implementation flows.

Strong leadership and communication skills with the ability to work effectively with global, cross-functional distributed teams across architecture, RTL, CAD, circuit design, physical design, SoC, and verification disciplines.

Proficiency in scripting and automation to improve productivity, debug efficiency, and design-flow scalability, including the adoption of GenAI-driven initiatives where applicable.

Scripting to automate tasks and improve debug efficiency including genAI initiatives.

Experience working with industry-standard EDA implementation and signoff flows for physical design, timing analysis, power analysis, and physical verification.

Minimum Qualifications Candidates should typically have one of the following:

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science , or a related technical field with relevant experience in hardware engineering, CPU design, physical design, clock design, or implementation.

ORMaster’s degree in Electrical Engineering, Computer Engineering, Computer Science , or a related technical field with relevant experience in hardware engineering, CPU design, physical design, clock design, or implementation.

ORPhD in Electrical Engineering, Computer Engineering, Computer Science , or a related technical field with relevant experience in CPU design, physical implementation, clock design, or circuit-aware methodology.

The role is intended for experienced candidates and is open for Staff Engineer level.

Preferred Qualifications Experience in any of the following areas would be highly valuable:

Experience leading or contributing to CPU, GPU, or large SoC physical design integration from early floor planning through final GDS tapeout.

Strong background in top-level or chip-level physical design, including floor planning, partitioning, pin placement, power planning, clock distribution, IP…