Formal Verification Senior Engineer

Company:

Qualcomm Technologies International Ltd

Engineering Group, Engineering Group > ASICS Engineering

• Develop deep understanding of 3D Graphics hardware pipeline, feature sets, data paths, block functionalities & interfaces;
  Prior knowledge of GPU Architecture is a big plus.
• Hands-on experience in strategizing, brainstorming, and developing Formal Property Verification (FPV) test-plan, developing an assertion-based verification testbench, debugging all RTL artefacts, and achieving formal sign-off matrices is a MUST.
• Collaborate with global GPU RTL design and DV teams to achieve the project goals.
• Required proficiency with industry standard formal tools, hands-on experience writing System Verilog Assertions, solving formal proof complexity by applying various abstraction techniques, deep bug-hunting, coverage closure and achieving sign-off.
• Hands-on experience in other formal applications like DPV, C2
  
  RTL SEQ, RTL2
  
  RTL SEQ, etc. is a plus.
• Strong communication skills, ability to learn, improve, and deliver

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field.

Bachelors/Masters in Electronics/Computer Engineering

2+ years of relevant experience in Formal Verification

Formal Property Verification (FPV), DPV, C2

RTL, System Verilog, System Verilog Assertions (SVA), Jasper Gold, VC Formal

* References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

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