RISC-V Debug, Trace & Profiling IP Architect
Listed on 2026-10-16
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Engineering
Hardware Engineer, Systems Engineer
SiFive is seeking a hardware design engineer in Cambridge with a passion for developing advanced debug, trace, and profiling hardware. This role involves collaborating with cross-functional teams to design high-performance hardware that supports RISC-V architecture.
The ideal candidate will have over 7 years of experience in RTL design, strong proficiency in Verilog or VHDL, and a Master's or PhD in a related field. SiFive promotes diversity and an inclusive work environment.
As a RISC-V Debug, Trace & Profiling IP Architect, you will play an important part at SiFive in Cambridge, England, United Kingdom.
This opportunity is part of our work in Engineering.
The advertised compensation is 60.000 - 90.000.
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
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