Senior​/CPU Physical Design Engineer Compute​/Semiconductors

We are partnered with a global leader in semiconductor and wireless technology innovation. The team is looking to hire a Senior or Staff Server CPU Physical Design Engineer to own block-level physical implementation for next-generation, high-performance custom CPU cores targeting advanced compute and server-class platforms.

This is a permanent, fully onsite opportunity based in Cambridge, UK.

• Own or contribute to CPU block implementation from RTL/netlist to GDS
• Drive timing closure and physical implementation convergence across multiple modes, corners, and operating conditions.
• Debug and resolve complex implementation issues across timing, congestion, clocking, IR drop, power integrity, EM, and DRC/LVS.
• Collaborate with RTL, architecture, circuits, CAD, SoC, and post-silicon teams to improve design quality and PPA.
• Develop and enhance physical design flows, automation, and methodologies.

• Strong experience in physical design — synthesis, floor planning, placement, CTS, routing, timing closure, ECOs, and signoff.
• Solid understanding of STA and timing closure methodologies, including PPA trade-offs.
• Hands-on experience with industry-standard EDA tools — Genus, Innovus, Fusion Compiler, Prime Time, Tempus, Voltus, Red Hawk, or equivalent.
• Scripting experience in TCL, Python, or Perl.
• Experience on CPU cores, advanced nodes (7nm and below), or low-power design techniques advantageous.

/ Physical Design / Place & Route / Floor planning / CTS / Timing Closure / STA / ECO / Synthesis / Innovus / Fusion Compiler / Prime Time / Tempus / Voltus / Red Hawk / DRC / LVS / Low Power / CPU / High Performance Compute / Advanced Nodes / TCL / Python

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