FPGA Engineer - VHDL, Artix-, Timing Closure
Listed on 2026-10-16
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Engineering
Hardware Engineer, Electronics Engineer, Systems Engineer
Platform Recruitment is seeking an Electronic FPGA Engineer in Cambridge to join a collaborative engineering culture. You will design FPGA logic in VHDL for Xilinx Artix-7 devices using Vivado and develop FSMs to control hardware interfaces.
You will also implement I2C/SPI drivers, write self-checking test benches, perform simulations, and bring-up hardware in lab settings, ensuring timing closure and robust documentation.
This posting is for the FPGA Engineer - VHDL, Artix-7, Timing Closure role at Platform Recruitment, based in Cambridge, England, United Kingdom.
This opportunity is part of our work in Engineering.
The advertised compensation is 65.000 - 95.000.
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the FPGA Engineer - VHDL, Artix-7, Timing Closure role in the description above.
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