Senior IC Layout Engineer; Hybrid Speed Analog IP
Listed on 2026-10-16
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Engineering
Electronics Engineer, Systems Engineer, Hardware Engineer
IC Resources in Cambridge is seeking a Senior IC Layout Engineer to own the custom layout and verification of analog circuits, blocks, and IP for multi-Gigabit Ser Des and memory IO. The role offers hybrid working with 3 days in the office.
You will lead chip layout activities and benefit from opportunities for career progression, with experience in high-speed designs valued. Tools include Cadence Virtuoso, Spectre/HSpice and Calibre across advanced nodes.
The Senior IC Layout Engineer (Hybrid) – High-Speed Analog IP role at IC Resources is now open for applications in Cambridge, England, United Kingdom.
If your experience matches this role, we encourage you to apply.
All applications are reviewed carefully by our team.
The position is based in Cambridge, England, United Kingdom.
This opportunity is part of our work in Engineering.
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