Post-Silicon Debug Tools Engineer

Job Overview

Arm's Central Engineering DFT Architecture and Methodology team defines the future of Design-for-Test across Arm's CPUs, GPUs, System IP, AI accelerators and next-generation SoCs. The team develops DFT architectures, methodologies and implementation flows that enable high-quality, scalable test solutions across soft IP, hard macros, test chips and complex multi-die SoCs.

Arm's Central Engineering DFT Architecture and Methodology team defines the future of Design-for-Test across Arm's CPUs, GPUs, System IP, AI accelerators and next-generation SoCs. The team develops DFT architectures, methodologies and implementation flows that enable high-quality, scalable test solutions across soft IP, hard macros, test chips and complex multi-die SoCs. Working at the forefront of semiconductor innovation, you will collaborate with product teams, system architects, design engineers and EDA vendors to shape DFT technologies several years ahead of production.

This is a highly technical architecture role with significant influence across Arm and the broader semiconductor ecosystem.

• Define DFT architecture for next-generation Arm IPs and SoCs, including emerging AI and hyperscale computing products.
• Develop and drive scalable DFT methodologies and implementation flows used across multiple Arm engineering organizations.
• Evaluate emerging DFT technologies and lead technical investigations to solve future product challenges.
• Collaborate with architecture, implementation, verification and physical design teams to define robust DFT solutions.
• Work closely with EDA vendors to influence product roadmaps, evaluate new capabilities and drive adoption of new technologies.
• Produce architecture specifications, methodology documentation and deployment guidance.
• Provide technical leadership and mentorship across project teams.
• Support strategic engagements with customers, ASIC partners and industry standards bodies where appropriate.
• Contribute to technical publications, patents and industry conferences.

• Principal or Senior Principal level engineer with extensive experience in Design-for-Test architecture and implementation.
• Strong understanding of modern SoC DFT methodologies including:
• Scan architecture and scan compression
• ATPG and fault simulation
• At-speed testing
• Memory BIST
• Logic BIST
• JTAG / IEEE 1149.1
• IJTAG / IEEE 1687
• DFT verification and debug
• Experience developing reusable DFT methodologies or automation rather than project-specific solutions.
• Experience evaluating and deploying Siemens Tessent, Synopsys and/or Cadence DFT solutions.
• Strong scripting skills (Perl, Tcl and/or Python) together with Linux/Unix expertise.
• Excellent problem-solving and analytical skills.
• Strong communication skills with the ability to influence technical direction across multiple engineering teams.
• Degree (or equivalent) in Electronic Engineering, Computer Engineering or related discipline.

• Experience defining DFT architecture for large-scale SoCs.
• Experience with heterogeneous compute systems, AI accelerators or hyperscale computing products.
• Knowledge of IEEE 1500, IEEE 1838 and advanced IJTAG methodologies.
• Experience with Streaming Scan Network (SSN) and chiplet/3
  
  DIC architectures.
• Familiarity with silicon bring-up and production test.
• Experience working directly with EDA vendors on new technology development.
• Knowledge of synthesis, STA and physical implementation considerations for DFT.
• Experience with formal verification and simulation methodologies.
• Record of patents, conference publications or contributions to industry standards.

Please note that a relocation package (including visa sponsorship support) is available for this role, for candidates who require it.

At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email  . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation.

Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment…