SoC ASIC​/FPGA Design Engineer - RTL, C​/C++, Python

A technology company in Cambridge is seeking an ASIC Hardware Engineer to join their advanced semiconductor team. The ideal candidate will have a strong background in ASIC and/or FPGA design, along with programming experience in C/C++ and Python. Candidates should be knowledgeable about GPU, CPU, DSP, or FPU architectures. This role promises an exciting opportunity for career advancement within a leading organization focused on cutting-edge technologies.
This posting is for the SoC ASIC/FPGA Design Engineer - RTL, C/C++, Python role at Edison Smart®, based in Cambridge, England, United Kingdom. We aim to respond to suitable candidates as soon as possible. Full responsibilities and requirements are described in the listing above. Learn more about the SoC ASIC/FPGA Design Engineer - RTL, C/C++, Python role in the description above.

We appreciate your interest in this position.