Senior IC Layout Engineer — Hybrid, -Speed SerDes
Listed on 2026-10-16
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Engineering
Electronics Engineer, Systems Engineer, Hardware Engineer
IC Resources in Cambridge is seeking a Senior IC Layout Engineer to own custom analog layout and verification of circuits, cells, blocks, and IP for high-speed Ser Des and memory IO in advanced semiconductor technology nodes. Hybrid working is available with 3 days a week in the office.
The ideal candidate will have a strong background in analog IC layout, particularly on high-speed designs, with proficiency in Cadence Virtuoso, Spectre/HSpice, Calibre/PVS, and parasitics extraction.
Step into the Senior IC Layout Engineer — Hybrid, High-Speed Ser Des role at IC Resources in Cambridge, England, United Kingdom and grow with us.
The position is based in Cambridge, England, United Kingdom.
This opportunity is part of our work in Engineering.
The advertised compensation is 70.000 - 95.000.
We aim to respond to suitable candidates as soon as possible.
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