DFT Engineer

About Graphcore

At Graphcore, we’re building the future of AI compute. We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale. As part of the Soft Bank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing Soft Bank AI ecosystem.

To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world. We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence.

Graphcore’s experienced, skilled, and motivated engineering team is heavily involved in shaping the future of AI. A successful candidate will exhibit exceptional knowledge in Design for Testability (DFT) and will have a strong technical background and experience in DFT methodologies, complemented by a robust, self-motivated work ethic. The ideal candidate should also have a focus on quality and demonstrate a good understanding of the importance of production test on the success of a product.

Some hands-on experience in one or more of the following areas is essential: RTL design, simulations and debugging, synthesis, STA.

We are expanding and looking for an experienced DFT engineer to join the Silicon team. As a part of our team, you will have the opportunity to work on next-generation AI designs targeted for data centres applications.

• Keep up with the latest industry trends in DFT domain and help adopt the latest DFT techniques and methodologies
• Work closely with design, verification, physical design and product engineering teams to integrate DFT requirements into the overall design process
• Define and implement DFT architecture and features for next-generation AI designs and support their verification effort
• Develop efficient DFT flows and methodology compatible with silicon design flows
• Work with 3rd party IPs to integrate the provided design into the DFT infrastructure
• Generate structural test vectors, analyze and improve test coverage
• Work with the product and test engineering teams to ensure successful silicon bring-up and help identify any silicon failures to enhance yield learning and improvement

• Very good understanding of DFT components like JTAG (IEEE 1149.x), IJTAG (IEEE P1687), Core Test (IEEE P1500), SSN (Streaming Scan Network), Test Compression, OCC etc.
• Experience on developing DFT specifications and driving the implementation of the DFT features
• Experience in MBIST and BISR implementation and verification is desired
• Solid understanding of design verification methodologies for validating the DFT features using simulation in pre-silicon designs
• Exposure to STA constraints development and analysis for DFT modes and SDF simulations would be a plus
• Experience in Scan based testing and industry standard ATPG tools
• Knowledge of ATPG pattern verification and gate-level simulation flows using Synopsys VCS and Verdi or other EDA tools
• Very good knowledge of Digital Integrated Circuits and Systems
• Hands-on experience with Verilog RTL coding and familiarity with System Verilog
• Strong scripting and debugging skills using programming languages like Python, TCL, Perl, Shell etc.
• Exposure to silicon bring-up, post-silicon testing and tester pattern debugging
• Strong problem-solving skills across various levels of design hierarchies
• Great team working and communication skills

• Bachelors or Mastersor PhD in Computer engineering/Electrical engineering/Electronics Engineering

In addition to a competitive salary, Graphcore offers…