SoC ASIC​/FPGA Design Engineer - RTL, C​/C++, Python

A technology company in Cambridge is seeking an ASIC Hardware Engineer to join their advanced semiconductor team. The ideal candidate will have a strong background in ASIC and/or FPGA design, along with programming experience in C/C++ and Python. Candidates should be knowledgeable about GPU, CPU, DSP, or FPU architectures. This role promises an exciting opportunity for career advancement within a leading organization focused on cutting-edge technologies.
Our group is growing, and we are hiring a SoC ASIC/FPGA Design Engineer - RTL, C/C++, Python in Cambridge, England, United Kingdom. Are you ready to take on the SoC ASIC/FPGA Design Engineer - RTL, C/C++, Python role at Edison Smart®? We would love to welcome a new SoC ASIC/FPGA Design Engineer - RTL, C/C++, Python to our group in Cambridge, England, United Kingdom.